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MC74HCT04A Hex Inverter
With LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS
The MC74HCT04A may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. The HCT04A is identical in pinout to the LS04.
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14 PDIP-14 N SUFFIX CASE 646 MC74HCT04AN AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 1 14 A1 1 2 Y1 TSSOP-14 DT SUFFIX CASE 948G HCT 04A ALYW HCT04A AWLYWW
* * * * * * *
Output Drive Capability: 10 LSTTL Loads TTL/NMOS-Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5V Low Input Current: 1A In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 48 FETs or 12 Equivalent Gates
LOGIC DIAGRAM
A2
3
4
Y2
A3
5
6
Y3 Y=A
1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
A4
9
8
Y4
Pin 14 = VCC Pin 7 = GND
FUNCTION TABLE
Inputs Outputs Y H L
A5
11
10
Y5
A L H
A6
13
12
Y6
Pinout: 14-Lead Packages (Top View)
VCC 14 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8
ORDERING INFORMATION
Device MC74HCT04AN MC74HCT04AD MC74HCT04ADR2 Package PDIP-14 SOIC-14 SOIC-14 TSSOP-14 TSSOP-14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel
1 A1
2 Y1
3 A2
4 Y2
5 A3
6 Y3
7 GND
MC74HCT04ADT MC74HCT04ADTR2
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 7
Publication Order Number: MC74HCT04A/D
MC74HCT04A
IIIIIIIIIIIIIIIIIIII II I IIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature Range - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
Symbol VCC Parameter Min 4.5 0 Max 5.5 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 1) VCC - 55 0 + 125 500
_C
ns
tr, tf
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MC74HCT04A
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC V 4.5 5.5 4.5 5.5 4.5 5.5 |Iout| 4.0mA 4.5 4.5 5.5 |Iout| 4.0mA 4.5 5.5 5.5 Guaranteed Limit -55 to 25C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 1 85C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 10 125C 2.0 2.0 0.8 0.8 4.4 5.4 3.70 0.1 0.1 0.40 1.0 40 A A V Unit V V V
Symbol VIH VIL VOH
Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage
Condition Vout = 0.1V |Iout| 20A Vout = VCC - 0.1V |Iout| 20A Vin = VIL |Iout| 20A Vin = VIL
VOL
Maximum Low-Level Output Voltage
Vin = VIH |Iout| 20A Vin = VIH
Iin ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current
Vin = VCC or GND Vin = VCC or GND Iout = 0A Vin = 2.4V, Any One Input Vin = VCC or GND, Other Inputs GND i Iout = 0A
ICC
-55C 5.5 2.9
25 to 125C 2.4 mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + ICC.
AC CHARACTERISTICS (VCC = 5.0V 10%, CL = 50pF, Input tr = tf = 6ns)
Guaranteed Limit Symbol tPLH, tPHL tTLH, tTHL Cin Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance -55 to 25C 15 17 15 10 85C 19 21 19 10 125C 22 26 22 10 Unit ns ns pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Inverter)* 22 pF * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HCT04A
tf 2.7V 1.3V 0.3V tPLH 90% OUTPUT Y 1.3V 10% tTLH tTHL tPHL tr 3.0V
INPUT A
GND
Figure 1. Switching Waveforms
TEST POINT OUTPUT DEVICE UNDER TEST CL*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
A
Y
Figure 3. Expanded Logic Diagram (1/6 of the Device Shown)
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MC74HCT04A
PACKAGE DIMENSIONS
PDIP-14 N SUFFIX CASE 646-06 ISSUE L
14 8
B
1 7
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
A F C N H G D
SEATING PLANE
L
J K M
SOIC-14 D SUFFIX CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC74HCT04A
PACKAGE DIMENSIONS
TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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EE CC EE CC
A -V-
MC74HCT04A
Notes
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MC74HCT04A
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MC74HCT04A/D

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